Architectures for High Performance, High Confidence, and Low Power

Continuing hardware enhancements governed by Moore’s law can provide faster and plentiful transistors. However, their power consumption and susceptibility to transient faults are raising serious concerns. Our research is looking to architect the hardware for the three-pronged goals of performance, power and reliability in a cost and complexity effective manner, by identifying what mechanisms to provide in the hardware and how to exploit these mechanisms in software.