Location March 7, 2009 Hamilton Crowne Plaza, Washington DC, USA Important Dates Submission due: Dec 15, 2008 11:59 PM (PST)(No Extension) Notification to authors: Jan 25, 2009 Final copy deadline: Feb 10, 2009 Workshop Organizers Co-Organizers Bhuvan Urgaonkar, Penn State Sudhanva Gurumurthi, University of Virginia Web and Publicity Chair Byung Chul Tak, Penn State Program Committee Frank Bellosa, University of Karlsruhe Mahmut Kandemir, Penn State Chul Lee, Samsung Electronics Mircea Stan, University of Virginia Tom Wenisch, University of Michigan

Overview We are in the era of data-centric computing. The massive growth in the volume of digital data poses new challenges for the design and management of storage systems across a diverse set of computing platforms, from sensors and personal computers to high-end servers and even entire data centers. While hard disk drives have served as the de-facto storage medium for decades, the performance limitations and power consumption due to the inherent mechanical nature of these devices pose large hurdles for their continued use in future data-centric computing platforms. Furthermore, with the advent of multi-core processors, the gap between the I/O demands of the cores and the capability of disk-based storage systems is rapidly widening. The emergence of solid-state storage devices provides opportunities to address these performance and power challenges. There are a variety of solid-state technologies, such as, Flash, Magnetoresistive RAM (MRAM), and Phase Change Memory (PCM), each of which has unique characteristics with regard to read/write latency, power, reliability, and cost. There are a variety of ways to leverage solid-state technology and integrate them into the storage hierarchy. These hybrid systems might employ solid-state memory in a variety of ways, such as capacity extensions to traditional DRAM-based main memory, caches or buffers that retain data over longer time scales, devices that complement or replace hard disk drives, or some combination of these approaches. The non-volatile nature of these devices also opens up possibilities for new programming models. Ongoing efforts from industry to make solid-state memory more affordable, durable, and lower latency opens up new opportunities as well as challenges for computer architects, systems software designers, and application developers. Utilizing solid-state technology effectively requires close interaction between researchers in these communities. The objective of this first WISH workshop is to create a forum for such interaction. Towards this end, we solicit papers that present new research results, describe works in progress, or propose new directions of research. We also welcome position papers from industry. We take a broad view of hybrid storage and welcome research from a variety of communities---hardware designers, architects, designers of systems and application software, among others. Submission Instructions Submissions are solicited by 11:59pm EST December 15, 2008. A submission must be no longer than 8 pages including figures, tables, and references. Text should be formatted in two columns on 8.5-inch by 11-inch paper using 10 point fonts and 1-inch margins. Author names and affiliations should appear on the title page (reviewing is not blind). Pages should be numbered, and figures and tables should be legible in black and white without requiring magnification. Papers not meeting these criteria will be rejected without review, and no deadline extensions will be granted for reformatting. Authors will be notified via e-mail about the acceptance of their manuscripts. Please contact the program co-organizers in case of any questions or clarifications regarding your submission. To submit a paper, send it via email, as a PDF file, to this address: wish2009submissions@cse.psu.edu