Location March 7, 2009 Hamilton Crowne Plaza, Washington DC, USA Important Dates Submission due: Dec 15, 2008 11:59 PM (PST)(No Extension) Notification to authors: Jan 25, 2009 Final copy deadline: Feb 10, 2009 Workshop: Mar 7, 2009 Workshop Organizers Co-Organizers Bhuvan Urgaonkar, Penn State Sudhanva Gurumurthi, University of Virginia Web and Publicity Chair Byung Chul Tak, Penn State Program Committee Frank Bellosa, University of Karlsruhe Mahmut Kandemir, Penn State Chul Lee, Samsung Electronics Mircea Stan, University of Virginia Tom Wenisch, University of Michigan

Invited Talk Details Integrating NAND Flash into the Storage Hierarchy ... Research or Product Design? by Frank Hady, Intel NAND Flash based storage has entered the storage hierarchy as both Solid State Drives (SSD) and Hard Disk Drive (HDD) caches. This talk will briefly describe the capabilities of both SSD and cache solutions currently available focusing on the system level impact of each. This fundamental change to the existing storage hierarchy brings with it a number of potentially high impact research opportunities. We'll discuss six different potential areas of research: Flash Translation Layer (FTL) design for performance, FTL design for lifetime, OS I/O scheduling, application storage usage, DAS vs. SAN/NAS, and new storage hierarchies. Together we'll look at each from a researcher's perspective to separate the wheat - research opportunities - from the chaff - product design. Speaker Bio Frank Hady Senior Principal Engineer Director of Network Storage Pathfinding Storage Technology Group Intel Corporation Dr. Frank Hady is a Senior Principal Engineer in the Storage Technology Group at Intel. He leads a pathfinding group researching the platform impact from the introduction of disruptive storage technologies like Flash based storage. His group is also researching distributed home storage advances to enable the extension of the C: experience to media and data stored anywhere in the home with tightly synchronized cross-home media playback. Prior to this, Frank researched converged comms/compute architectures for Intel - pioneering key parts of Intel's Quick Assist Integrated Accelerator technology. In the 90's Frank drove substantial industry chipset performance advances, and brought Intel design together with industry use for key I/O busses like PCI and AGP delivering increased platform performance. He joined Intel in 1995 from the Supercomputing Research Center where he built parallel computers and researched improvements to their networks. Frank has authored over 25 publications and industry standards, and has over 20 patents granted and pending. Frank received his BS and MS in EE from the University of Virginia, and his PhD from the University of Maryland in 1993.